The invention relates in general to diagnostics for computer equipment and in particular to diagnostics for computer chips.
Debug ports are pins situated on chips as dedicated pins for driving data from a subject chip at the clock of a system processor. These ports are not used by the system within the chip, but are used by engineers for debugging or for obtaining information about the internal workings of a chip. Most commonly, engineers use these debug ports in preparation of diagnostic tests which are used to address flaws, referred to as issues, which occur in, e.g., general purpose integrated circuits (xe2x80x9cICsxe2x80x9d), specialized ICs (i.e., Application Specific Integrated Circuits xe2x80x9cASICsxe2x80x9d), and processors (i.e., Central Processor Units xe2x80x9cCPUsxe2x80x9d). Design errors tend to be the most common type of issue, and they may exist on the chip itself or in the software that is being used within the computer system in which the chip is utilized.
There are generally three types of hardware issues: functional design defects, electrical design defects, and manufacture design defects. These ports are also useful in addressing other issues, such as those based on manufacturing shorts, gaps that occur in the chip where an electrical connection is not made properly, or for addressing errors involving unwanted electrical connections made between two points. Chips are increasingly complicated in design, and accordingly, there are an increasing number of potential flaws in chip technology, thereby necessitating a corresponding rise in the complexity and the use of debug ports. As such, the actual control and manipulation of debug ports has become even more problematic, as each given situation requires different information to be driven out by the pins at different times, in accordance with specific user needs.
Prior art solutions present the user with a choice of methods for controlling the data which is sent to the debug port. One particular prior art solution for this control offers only single mode or unilateral control, (i.e., accessing either the internal control or external control but not both), where the user has one option or method for controlling the interface and the debug port. Different ways for implementing this control are available including monitoring via external control lines (such as user set Dual Inline Package xe2x80x9cDIPxe2x80x9d switches) or by driving information onto the chip through jumper blocks or pull-up resistors. These control lines use an external interface to tell the chip what data to drive to the debug port, whether these data are from a particular portion of the chip, or from a selected register.
Another prior art option involves control via logic inside the chip itself, and/or setting configuration information through software control of internal registers. The internal control of the prior art employs software to set register values, thereby controlling what data is sent out to the port from the inside. In this method, there are no specific In/Out (xe2x80x9cI/Oxe2x80x9d) pins dedicated to controlling the debug port but instead, a specific software application is written to modify data in control registers on the chip, either directly or through a scan interface such as Joint Test Action Group xe2x80x9cJTAGxe2x80x9d.
In any case, prior art solutions involve only one of external or internal solutions. Each of the described prior art methodologies has its own advantages and disadvantages, and, depending on the requisite application, having access to only one type of control has proved insufficient for the user. While some prior art solutions have actually attempted to provide both internal and external control, it has been assumed that it was difficult for the user to know for certain, at any given time, which method had been used by the chip in reporting the data. Thus, any attempts at control of the functionality in the chip were necessarily limited to the fact that no information relating to control is actually provided by the chip at any time. Hence, there is a risk danger that when using the aforementioned approach, that a user may log erroneous data due to a misunderstanding as to what exactly had been done to control that functionality. Furthermore, depending on how the chip itself is designed, it might be possible, for example, for one to set the external control lines to a certain value without realizing that it was being overridden by a piece of software that was being run, thereby further increasing the chance of flawed analysis.
In sum, each of the prior art solutions are lacking in user flexibility, have a high chance of error propagation due to user error, or will result in the need for a higher pin count from dedicated diagnostic pins. Hence, there is a need for a system and method which avoids the shortcomings of the prior art solutions and offers the opportunity for the accurate collection of data from subject chips.
These and other objects, features and technical advantages are achieved by a system and method which uses shared pins to drive external configuration data onto the chip and then, if the configuration is through software control or some other internal control method inside the chip, to drive the data back out onto the same line so that there need only be a single monitor point. In doing so, a single point can be monitored so that it is possible to know at all times what data are seen by a subject chip. This is accomplished through a drive hierarchy which dictates which control method will prevail such that, if multiple control methods are employed (or if a monitor attempts simultaneous usage of multiple control methods), one method will prevail over the others under the inventive hierarchy. Accordingly, the drive hierarchy is a planned scheme which is set so that regardless of which method is actually used, the data will be properly reflected on the lines through a ratio of impedance and pull resistance.
One embodiment involves the use of simultaneous control schemes, both internal and external, to set the external control through a three position switch, where the control lines could be driven high, low, or left floating, (i.e., driven neutral). In this case, if the monitor recognized that it would be better to use internal control, the monitor would set the switch to the middle position, where the line was not driven either way. This would allow the chip to drive the information therefrom on the same lines as it was driven in, so that the relevant data could be logged as being the configuration being used by the chip. This has a slight advantage, in that it allows the monitor to log the information with regards to configuration. Yet another embodiment might involve dedicating extra pins on the chip for driving out configuration information only. One possible solution therein is the use of two sets of pins, one set for driving in configuration information and another for driving out the actual status information. The output from the actual status information will be considered to be the final value. However, this embodiment requires additional pins and both of the above embodiments can yield different data, regardless of the particular control employed thereon.
Thus, in an especially preferred embodiment, the inventive system provides for a logic analyzer or other processor to receive data from a single port on the chip (or ASIC) which is being tested. The inventive system further permits the monitor to receive the information from a port which includes both data being transferred out of the chip in the debugging processes, and information relating to the configuration of the debugging process (e.g., an indication as to which needed from within the chip are the sources of the given information). The resulting descriptive information may arrive from hardware configuration on a subject chip, or may be the result of a software override of that hardware. Under either embodiment, the inventive solution provides that the receiving processor receives accurate data, based on a proprietary hierarchy which has been implemented prior to the logic analyzer receiving it.
An important advantage of the inventive system described herein is that it provides an error free reading of the internal state of the chip through a single monitor point, thereby eliminating uncertainty in analysis and avoiding the need for additional pins. Also, the inventive system further provides for the advantage of avoiding the possibility of electrical damage (which might occur where, say, a user tries to pull too much current from the driver). Moreover, the present invention provides the advantage of allowing the usage of both internal and external methods of control. Provision of such allows the user to adjust for prevailing diagnostic preferences, while offering the easiest methodology by which to run the diagnostics. Accordingly, the inventive system is user friendly yet flexible. Moreover, the reduction of user error and the potential impact of user error in the present invention offers a more time efficient testing schedule for a monitor. Also, the present invention yields the possibility of providing more functionality, both on chip and off chip, in terms of monitor control of diagnostic functionality.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.